The present invention relates generally to silicon-on-insulator (SOI) structures, and more specifically to a fully depleted SOI structure formed on a silicon-on-insulator substrate which includes tungsten damascene contacts.
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and xe2x80x9coffxe2x80x9d state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance and xe2x80x9coff statexe2x80x9d leakage problem as well as obtain reduced size, silicon-on-insulator technology (SOI) has been gaining popularity. SOI technology employs a thin silicon device layer of monocrystalline silicon material overlying an insulating layer on a bulk wafer. The structure can be formed by a number of well-known techniques, such as zone melting and recrystallization (ZMR), separation by implanted oxygen (SIMOX), or Bonded and Etchback (BESOI).
Field effect transistors fabricated in the silicon device layer have many advantages over bulk silicon FETs fabricated in the traditional bulk silicon substrates including resistance to short-channel effect, steeper subthreshold slopes, increased current drive, higher packing density, reduced parasitic capacitance, and simpler processing steps.
These advantages combined with the continually increasing cost of bulk silicon submicron integrated circuit processes and the lower complexity/cost of SOI integrated circuit processes, SOI technology shows great potential to become the low cost mainstream production technology.
Despite the advantages, there are problems with SOI technology which limit its performance. Unlike bulk silicon FETs, the body of an SOI FET is usually electrically floating. In a non-fully depleted FET (e.g. the silicon film thickness is greater than the maximum channel depletion width), carriers (holes in n-channel FETs and electrons in p-channel FETs) generated by impact ionization accumulate near the source/body junction of the FET. Eventually sufficient carriers will accumulate to forward bias the body with respect to the source thus lowering the threshold voltage through the body-bias effect. Extra current will start flowing resulting in a xe2x80x9ckinkxe2x80x9d in the I-V characteristics. This reduces the achievable gain and dynamic swing in analog circuits, and gives rise to abnormality in the transfer characteristics in digital circuits.
In a fully-depleted SOI FET (e.g. silicon film thickness that is less than the maximum channel depletion width), the channel is depleted completely under normal operations. The source/channel junction has a lower potential barrier, and the carriers generated by impact ionization have smaller effect on the body and channel potential, thus the xe2x80x9ckinkxe2x80x9d softens.
However, in fully-depleted FETs, the depletion charge is reduced for a given body doping concentration, leading to a smaller threshold voltage. Threshold voltage becomes very sensitive to variations in the silicon film thickness and therefore, fabrication of high performance circuits can be very difficult. Additionally, the reduction of silicon film thickness in a fully-depleted FET gives rise to high source/drain series resistance which in turn lowers the operating speed of the device. One solution to the series resistance problem is to selectively reduce the silicon film thickness over the channel region. However, the resulting recessed region and the polysilicon gate are not automatically aligned. To allow for the possible misalignment, the recessed thin silicon region must be made longer than the gate. This reduces the device performance and density, and results in asymmetrical devices.
Accordingly, there is a strong need in the art for a semiconductor circuit structure, and a method for forming such structure, that includes a fully depleted channel to eliminate the xe2x80x9ckinkxe2x80x9d in the I-V curve but does not suffer the problems of poor output resistance and slowed operating speed. Further, there a need in the art for such a device which does not suffer possible misalignment caused by fabrication processes which do not automatically align the gate, source and drain regions of the FET.
A first aspect of the present invention is to provide a fully depleted field effect transistor (FET) with a tungsten damascene top gate. The FET is formed in a silicon on insulator substrate which includes a thin device layer positioned over an insulating layer. The FET comprises a body region formed in the silicon device layer and including a source region and a drain region of a first conductivity semiconductor on opposing sides of a central channel region of an opposite conductivity semiconductor. A base gate region is positioned above the central channel region and a wide top gate region comprised of tungsten damascene is spaced apart from the central channel region and positioned over the base gate region. The tungsten damascene forms a contact between the base gate region and metal layers of an integrated circuit utilizing the FET.
In the preferred embodiment, the central channel region is an inverted T-shaped central channel region with a narrow full depletion region adjacent the base gate region and a wide channel region adjacent the insulating layer. The narrow full depletion region may have a channel width that is less than a width of the base gate region and the wide channel region may have a width approximately equal to a width of the top gate region.
A second aspect of the present invention is to provide a semiconductor device comprising a plurality of fully depleted field effect transistors formed on a semiconductor substrate. Each fully depleted FET comprises: a) a body region including a source region and a drain region of a first conductivity semiconductor on opposite sides of a central channel region of an opposing conductivity semiconductor; b) an insulating layer positioned below the body region isolating the body region from the semiconductor substrate; c) a base gate region positioned above the central channel region; and d) a wide top gate region comprised of tungsten damascene and spaced apart from the central channel region.
The central channel region of each transistor may be an inverted T-shaped central channel region with a narrow full depletion region adjacent the base gate region and a wide channel region adjacent the insulating layer. The narrow full depletion region of each transistor may have a-channel width that is less than a width of the base gate region and the wide channel region of each transistor may have a channel width approximately equal to a width of the wide top gate region.
The semiconductor device may further include a plurality of isolation trench regions isolating the body region of each transistor from adjacent transistors and the substrate may be a semiconductor of the same first conductivity semiconductor as the central channel region.
A third aspect of the present invention is to provide a method of fabricating a fully depleted field effect transistor with a tungsten damascene top gate region. The fully depleted FET is formed in a silicon on insulator substrate including a thin device layer of a first conductivity semiconductor positioned over an insulating layer. The method comprises: a) isolating a body region in the device layer; b) forming a base gate region above the body region; c) doping a thin top portion of the body region on opposing sides of the base gate region to an opposite conductivity semiconductor as the first conductivity semiconductor; d) forming a layer of nitride over the base gate region and the body region of the device layer such that the nitride has a vertical thickness adjacent to the base region that is thicker than a vertical thickness across the surface of the body region; e) doping a deep portion of the body region on opposing sides of the base gate region to the opposite conductivity silicon to form an inverted T-shaped central channel region of the first conductivity semiconductor positioned between a source region and a drain region of the opposite conductivity semiconductor; and f) forming a wide tungsten damascene top gate region above the base gate region.
The step of forming the base gate region may include forming a polysilicon layer over the body region; forming a mask layer over the polysilicon layer; patterning the mask layer to define the base gate region; and etching the mask layer and the polysilicon layer to form the base gate region. The step of forming the wide tungsten damascene top gate region may include depositing a layer of TEOS over the layer of nitride; polishing the TEOS to expose an island of nitride over the base gate region; etching the nitride to form a well extending to the base gate region; and forming a diffusion barrier over the exposed base gate region and filling the well with tungsten damascene from the wide tungsten damascene top gate region.
The step of doping the deep portion may include implanting impurity ions utilizing a 15-25 KeV electric field and the step of doping the thin top portion may include implanting impurity ions utilizing a 10-20 KeV electric field.
The method of fabricating a fully depleted field effect transistor with a tungsten damascene top gate region may further include forming source and drain tungsten damascene contacts. Forming such contacts may include: a) etching the nitride to form a well over each of the source region and the drain region to expose the source region and the drain region; b) forming a titanium nitride diffusion layer over the exposed source region and drain region; and c) filling each of the wells with tungsten damascene to from the tungsten damascene contacts.